Director High Speed IO Architecture & Design

THE ROLE:

Lead a Hardware/Digital IP Design Engineering team, collaborating across AMD and partner to develop next-generation high-speed I/O technologies.

THE PERSON:

An experienced semiconductor IP leader with strong technical and managerial expertise, exceptional communication skills, and a proven ability to lead high-performing engineering teams.

KEY RESPONSIBILITIES:

• Provide technical leadership and direction for the hardware/digital semiconductor design engineering organization.
• Lead and manage a team of System, Digital hardware, front-end/RTL/logic designers.
• Manage and scale the design team to develop reusable IP supporting a multi products roadmap
• Collaborate with IP. Sub-System, and SoC architects to translate high-level requirements into microarchitecture and design implementation plans.
• Contribute to the definition of IP architecture & microarchitecture, circuit architecture, and digital subsystem blocks.
• Drive architectural decisions for next-generation products within committed system-architecture and power, performance, and area budgets.
• Represent the digital design organization in cross-functional architecture reviews, customer technical engagements, and foundry and EDA partner discussions.
• Mentor front-end digital designers and micro architects through design reviews, technical coaching, and silicon debug.
• Own high-level design planning, work breakdown, task assignment, progress tracking, schedule and priority management, performance reviews, talent development, and hiring.
• Partners with the peer engineering directors, program managers, architects, circuit and AMS teams, and physical-design leads to deliver high-quality results on schedule and against technical requirements.
• Proactively manages critical paths, dependencies, priorities, and overall program risk.
• Collaborate across analog design, custom digital design, AMS circuit architecture, AMS design verification, functional verification, physical design, and DFX teams across multiple geographies.
• Ensure strong cross-team alignment, engagement, and execution from architecture through production.
• Co-lead the silicon-success methodology, establishing first-silicon-success expectations, disciplined debug practices, and a clear path from characterization to production.
• Define and improve front-end development flows to increase execution efficiency, effectiveness, and quality.
• Establish and enforce design-flow best practices and quality standards to meet committed performance, power, reliability, area, and timing requirements.
• Work closely with physical-design and DFX teams to deliver complete RTL-to-GDSII designs.
• Co-own post-silicon planning and execution, including initial bring-up, platform validation, characterization, parameter optimization, and final productization.
• Contribute to IP production and bench-level test, characterization, and validation plans in partnership with post-silicon characterization and validation teams.
• Enable and support post-silicon workstreams through new product introduction.

PREFERRED EXPERIENCE:

• High-Speed IO subsystems (SerDes/Chip-To-Chip), high-speed interconnects, and IO sub-system/platform firmware
• Progressive experience in digital IO Sub-System IP hardware design and technical leadership.
• Strong engineering and people-management experience, including building, developing, mentoring, and leading distributed engineering/technical teams.
• Demonstrated success delivering complex digital-on-top IO Sub-System IPs (including mixed signal IPs) through high-volume production, including production tape-outs in advanced FinFET CMOS nodes.
• Expertise in developing low power, low latency, high-performance microarchitecture of IO Datapath between host and peripherals
• Demonstrated ability to concurrently manage complex IPs across multiple SOC programs.
• Deep knowledge and technical experience from architecture to implementation of High Speed IO (HSIO) & PHYs digital sub-systems.
• Strong knowledge of digital design methodologies, including clock-domain-crossing checks, reset checks, low-power design, synthesis, static timing analysis, and timing closure.
• Experience collaborating with physical-design and functional-verification teams to deliver complete RTL-to-GDSII designs.
• Embedded firmware development experience is an advantage.
• Strong analytical, problem-solving, decision-making, and organizational skills, with the ability to independently resolve complex technical and organizational challenges.
• Excellent written and verbal communication skills, including the ability to summarize complex issues for executives and engage deeply with architects and engineers.
• Demonstrated ability to manage, build and develop high-performing, diverse technical teams through strong mentoring, coaching, and performance management.
• Ability to establish durable working relationships and networks across functions and geographies.
• Highly self-motivated, detail-oriented, results-driven, and committed to disciplined engineering practices.
• Collaborative team player who actively develops personal leadership capability and supports the growth of others.

ACADEMIC CREDENTIALS:

• Master’s degree or Ph.D. in Electrical Engineering, Computer Engineering. Emphasis on IO sub-systems digital/hardware architecture and design including detailed knowledge of High-Speed IO subsystems (SerDes/Chip-To-Chip), high-speed interconnects, and IO sub-system/platform firmware

LOCATION: Santa Clara, CA

This role is not eligible for visa sponsorship.